Driving circuit for a field emission display

ABSTRACT

There is a driving circuit disclosed for a field emission display which can reduce the power consumption and thus improve the reliability of high voltage elements by reducing the swing width of the driving voltage necessary for driving the gate, cathode and anode lines arranged to the field emission display. The driving circuit comprises a first switching element arranged between any one line of the plurality of lines and a power supply terminal, for performing a switching operation; a second switching element connected to the first switching element in serial and to any one line of the plurality of lines, for performing a switching operation; a charge charging/discharging element for adjusting the quantity of charge in any one line, in accordance with the state of a control signal inputted thereto and the switching state of the second switching element; a first element controller for controlling a flow of charge to the any one line by switching-controlling the first switching element; and a second element controller for controlling a flow of charge to the any one line by switching-controlling the second switching element.

TECHNICAL FIELD

The present invention relates to a field emission display, and moreparticularly to a driving circuit for a field emission display fordriving gate, cathode and anode lines in the field emission display.

BACKGROUND ART

Field emission display (FED), which has been spotlighted as a new flatpanel display device, is similar to a cathode ray tube (CRT) in viewthat it displays a picture on a screen using electrons emitted. However,there is a technical difference therebetween in the point that the fieldemission display uses a cold electron emission, whereas the cathode raytube uses a thermal electron emission.

A typical field emission display has some hundreds to thousands of fieldemission devices for emitting electrons arrayed every pixel and displaysa picture on a screen by allowing electrons from the field emissiondevices to be impinged on an anode having a phosphor film coatedthereon.

As shown in FIG. 1, a field emission device composing the pixel of thefield emission display comprises a cathode connected to a cathodeelectrode (10), a gate (14) arranged at predetermined intervals on thecathode (12) and an anode (18) having a phosphor film (16) coated on therear surface thereof. The phosphor film (16) generates lightscorresponding to a quantity of electrons impinged thereon and permits apicture to be displayed on the screen. The anode (18) serves to attractelectrons emitted from the cathode (12) and is made of a transparentmaterial so that lights are projected on the phosphor film (16)therethrough.

Also, the cathode (12) is a cone shape of which the top portion forms amicrotip. Electrons are emerged from the microtip under the influence ofelectric fields formed between the cathode (12) and the gate (14). Thegate (14) of which voltage is lower than the voltage applied to theanode (18) causes electrons to be emitted from the microtip of thecathode (12), and the emitted electrons go toward the anode (18).

Now, the current to voltage characteristics of the field emission,display composed of such a conventional field emission device will bedescribed below. As shown in FIG. 2, when the field emission display isdriven, a cathode current is not substantially flowed until a voltage(V_(G) _(—) _(C)) between the gate and the cathode reaches to “V_(L)”,and thereafter when the voltage (V_(G) _(—) _(C)) becomes higher than“V_(L)”, a cathode current becomes sharply high as a diode'scharacteristic. In FIG. 2, “V_(H)” a driving voltage applied to the:gate is approximately 100 V, and “V_(L)” is about 80 V.

FIG. 3 is a block diagram explaining a driving operation of the panel ina conventional field emission display. As shown in FIG. 3, the panel(20) is a picture displaying region in which field emission devices ofpixel unit as depicted in FIG. 1 is arranged in a matrix type. A controlunit (22) receives a control signal and an image signal from outside andoutputs the corresponding control signal and image signal by controllingthem so as to be suitable for the panel characteristic. A gate driver(24), which is connected to a plurality of gate lines, receives acontrol signal from the control unit (22) and produces a signal forscanning the corresponding gate lines. Data driver (26), which isconnected to a plurality of data lines, converts the image signalreceived from the control unit (22) so as to be suitable for the panelcharacteristic and then outputs it to each pixel via the data lines.

According to FIG. 3, the gate driver (24) performs a high-voltageswitching to emit electrons wherever time when a predetermined gate lineis selected by the control signal of the control unit (22). At thistime, the data driver (26) outputs the image signal suitable for thepanel characteristic to the selected gate line. Accordingly, the desiredpicture is displayed on the panel.

Herein, the gate driver (24) or the data driver (26) receives alow-voltage signal from the shift register and uses a high voltageoutput terminal for transmitting a high voltage more than 100 V to thecorresponding line. The high voltage output terminal will be describedwith reference to FIG. 4.

FIG. 4 shows a circuit for driving one gate line or data line (cathodeline). The circuit according to FIG. 4 comprises a high voltage PMOSelement (P1), a high voltage NMOS element (N1) and a high voltage PMOSelement controller (24 a) for switch-controlling the high voltage PMOSelement (P1) by means of an input signal from a control logic (notshown). A drain contact point between the high voltage PMOS element (P1)and the high voltage NMOS element (N1) is connected to the gate line (ordata line) of the panel (20).

According to the conventional output terminal circuit having such aconstruction, as shown in FIG. 5, in accordance with the inputting of astart control signal which is shift-outputted in synchronous with aclock signal (Clk), the high voltage PMOS element (P1) and the highvoltage NMOS (N1) are switched conversely and drive the gate lines (forexample, n, n+1, n+2) in sequence. Herein, each gate line (n, n+1, n+2)is driven sequentially by a high voltage (V_(high)) (for example, 100 V)in a rising edge or a falling edge of the clock signal (Clk)

A consumption power (P_(conv)) in the outputting terminal of theconventional driver being operated as described above is represented bythe following Equation 1 which indicates a consumption power (P_(conv))in the outputting terminal of the gate driver.

P _(conv) =N·f·C _(Load) ·V _(high) ²  <Equation 1>

Wherein, N is the number of the gate lines of FED panel, f is a framefrequency, C_(Load) is a capacitance of one gate line, and V_(high) isthe width of voltage swing in the outputting terminal.

In the above Equation 1, if the width of voltage swing (V_(high)) is setto 100 V, then the consumption power (P_(conv)) is represented by thefollowing Equation 2.

P _(conv)=10000·f·C _(Load)  <Equation 2>

As seen from the above Equation 2, for the conventional gate driver,since the output voltage of its outputting terminal is fully swingingfrom 0V to V_(H) (for example, 100 V), the power consumption increase,thereby causing an integrating capacity of the gate driver circuit to bereduced when integrating it. Also, there is a problem that a high heatproduced by such a high power consumption deteriorates the reliabilityof high voltage elements. Such problems occur similarly in a drivercircuit for driving cathode and anode lines.

DISCLOSURE OF THE INVENTION

Accordingly, the present invention has been made in order to solve suchproblems encountered in the conventional art as described above, and theobject of the present invention is to provide a driving circuit for afield emission display which can reduce the power consumption and thusimprove the reliability of high voltage elements by reducing the swingwidth of the driving voltage necessary for driving the gate, cathode andanode lines arranged to the field emission display.

In order to achieve the above object, the driving circuit for a fieldemission display according an embodiment of the present invention ischaracterized in that in a driving circuit for a field emission displayhaving the panel on which a plurality of gate and cathode lines arearranged, the driving circuit comprises:

a first switching element arranged between any one line of the pluralityof lines and a power supply terminal, for performing a switchingoperation;

a second switching element connected to the first switching element inserial and to any one line of the plurality of lines, for performing aswitching operation;

a charge charging/discharging element for adjusting the quantity ofcharge in any one line, in accordance with the state of a control signalinputted thereto and the switching state of the second switchingelement;

a first element controller for controlling a flow of charge to any oneline by switching-controlling the first switching element; and

a second element controller for controlling a flow of charge to any oneline by switching-controlling the second switching element.

Also, the driving circuit for a field emission display according toother embodiments of the present invention is characterized in that thedriving circuit comprises:

a plurality of cells, each cell being connected to each of gate lines inone to one manner;

a shift register for sequentially transmitting a gate line selectingcontrol signal to the plurality of cells;

a capacitor switching control unit for transmitting a capacitorswitching control signal having a predetermined pulse width to theplurality of cells;

an external capacitor control unit for outputting a capacitor lowswitching signal having a predetermined pulse width; and

a charge charging/discharging element for performing a chargecharging/discharging operation by means of the capacitor low switchingsignal,

wherein said cells comprise a first switching element arranged between avoltage supply terminal and the corresponding gate line, for performinga switching operation; a second switching element connected to the firstswitching element in serial and to the corresponding gate line, forperforming a switching operation; a first element controller forcontrolling a flow of charge to the corresponding gate line byswitching-controlling the first switching element by means of the gateline selecting control signal; and a second element controller forcontrolling the corresponding gate line and a flow of charge to thecharge charging/discharging element by switching-controlling the secondswitching element by means of the capacitor switching control signal,

said shift register, said capacitor switching control unit and saidplurality of cells being integrated into one block;

said charge charging/discharging element being arranged one or more tothe outside of the block.

BRIEF DESCRIPTION OF THE DRAWINGS

Now, the embodiments of the present invention will be described indetail in conjunction with the accompanying drawings, wherein:

FIG. 1 is a schematic view showing a structure of a conventional fieldemission device;

FIG. 2 shows the current—voltage characteristics of the conventionalfield emission device;

FIG. 3 is a block diagram illustrating a panel driving operation of theconventional field emission device;

FIG. 4 is a circuit diagram of high voltage outputting terminal of thedriver as shown in FIG. 3;

FIG. 5 is a timing chart of the circuit of FIG. 4;

FIG. 6 is a driving circuit diagram for the field emission displayaccording to one embodiment of the present invention;

FIG. 7 illustrates one example in which the driving circuit for thefield emission display as shown in FIG. 6 has been integrated into anintegrated circuit as a cell unit;

FIG. 8 is a timing chart of the driving circuit for the field emissiondisplay as shown in FIG. 6;

FIG. 9 is a waveform view illustrating in detail a voltage change in thegate line in accordance with the present invention;

FIG. 10 is a driving circuit diagram for the field emission displayaccording to other embodiments of the present invention; and

FIG. 11 illustrates other examples in which the driving circuit for thefield emission display as shown in FIG. 6 has been integrated into anintegrated circuit as a cell unit.

BEST MODE FOR CARRYING OUT THE INVENTION

FIG. 6 is a driving circuit diagram for a field emission displayarranged to the gate line, which is depicted in order to illustrate thebasic concept of the present invention, and a circuit for driving onlyone gate line is illustrated to help understand the above-mentionedFigure.

The first switching element (28) is arranged between the high voltagesupply terminal (V_(high)) and the gate line (Gate_Line) and performs aswitching operation by means of the first high voltage elementcontroller (32). The first high voltage switching element is preferablycomposed of a high voltage PMOS transistor The first high voltageelement controller (32) turns on and off the first high voltageswitching element (28) in response to receive a gate line selectingcontrol signal (Gate_Control) outputted from a shift register (notshown), thereby controlling the flow of charge to the gate line(Gate_Line).

The second high voltage switching element (30) is connected between thegate line (Gate_Line) and a capacitor low switching signal(Cap_Low_Switching) via a charge charging/discharging element (C_(Ext)),and performs the switching operation by means of the second high voltageelement controller (34). Preferably, the second high voltage switchingelement (30) is composed of a high voltage PMOS transistor.

In a preferred embodiment of the present invention, even though thefirst and second high voltage switching elements (28, 30) are embodiedby the high voltage PMOS transistors, high voltage NMOS transistors canbe used as shown in FIG. 10, instead thereof.

The second high voltage element controller (34) controls a switching ofthe second high voltage switching element (30) in response to receive acapacitor switch control signal (Cap_Switch_Control), therebycontrolling the gate line (Gate_Line) and a flow of charge to the chargecharging/discharging element (C_(Ext)).

Herein, the gate line selecting control signal (Gate_control) is asignal for selecting a gate line to be scanned, and is converted toeither a high level or a low level in accordance with the period of aclock signal (Clock).

The capacitor switch control signal (Cap_Switch_Control), which is asignal for turning on the second switching element (30) in order totransmit a part of charge of the gate line (Gate_Line) to the chargecharging/discharging element (C_(Ext)), is raised to be preceded by apredetermined value (α) more than the gate line selecting control signal(Gate_Control) and its width is wider by ½ clock duration than thesignal (Gate_Control).

The capacitor low switching signal (Cap_Low_Switching), which is asignal having a predetermined width (0V˜V_(cap)) of voltage swing, isapplied to the charge charging/discharging element (C_(Ext)).

The internal circuit composed of the first and second high voltageelement controllers (32, 34) can be constructed to turn on each of thefirst and second switching elements (28, 30) in case that the gate lineselecting control signal (Gate_Control) and the capacitor low switchingsignal (Cap_Low_Switching), which are inputted to the controllers (32,34) respectively, are at their high level. The internal circuit can alsobe constructed to turn on each of the first and second switchingelements (28, 30) in case that the gate line selecting control signal(Gate_Control) and the capacitor low switching signal(Cap_Low_Switching), which are inputted to the controllers (32, 34)respectively, are at their low level.

The charge charging/discharging element (C_(Etx)) is arranged betweenthe input terminal of the capacitor low switching signal(Cap_Low_Switching) and the second high voltage switching element (30)and thus controls the quantity of charge in the gate line (Gate_Line) inaccordance with the state of the capacitor low switching signal(Cap_Low_Switching) and the switching state of the second high voltageswitching element (30).

FIG. 7 illustrates a state in which the driving circuit as shown in FIG.6 was integrated as a cell unit. As depicted, the first and secondswitching elements (28, 30) and the first and second high voltage PMOSelement controllers (32, 34) are integrated into a single block (36)with being formed as one cell unit, while a plurality of chargecharging/discharging elements (C_(Ext1), C_(Ext2)) are arranged to theoutside of the integrated block (36).

Herein, the gate line selecting control signal (Gate_Control) applied toeach of cells (44, 45, 46, 47, . . . ) is a signal outputted from theshift register (38), and the capacitor switching control signal(Cap_Switch_Control) is a signal outputted from the capacitor switchingcontrol unit (40).

The plurality of charge charging/discharging elements (C_(Ext1),C_(Ext2)) are controlled by the external capacitor control unit (42)connected to the capacitor switching control unit (40).

In FIG. 7, even though the capacitor switching control unit (40) and theexternal capacitor control unit (42) were separately integrated into thesingle block (36), it should be noted that the external capacitorcontrol unit (42) can be integrated into the capacitor switching controlunit (40).

Meanwhile, since the plurality of cells (44, 45, 46, 47, . . . ) use thecharge charging/discharging elements (C_(Ext1), C_(Ext2)) only when gatelines are selected, one charge charging/discharging element (C_(Ext1))or (C_(Ext2)) is shared with every odd-numbered or even-numbered cells.That is, the odd-numbered cells (44, 46, . . . ) share the chargecharging/discharging element (C_(Ext1)), and the even-numbered cells(45, 47, . . . ) share the charge charging/discharging element(C_(Ext2)).

More precisely, one end of the charge charging/discharging element(C_(Ext1)) is connected to one control end of the external capacitorcontrol unit (42), and other ends thereof are the odd-numbered cells(44, 46, . . . ). Also, one end of the charge charging/dischargingelement (C_(Ext2)) is connected to the other control end of the externalcapacitor control unit (42), and other ends thereof the even-numberedcells (44, 46, . . . ).

Accordingly, the charge charging/discharging elements (C_(Ext1),C_(Ext2)) connected to the odd-numbered cells (44, 46, . . . ) and theeven-numbered cells (45, 47, . . . ) are alternately driven by theexternal capacitor control unit (42), when gate lines of theodd-numbered lines and the even-numbered lines (output (1), output (2),output (3), output (4), in FIG. 7) are driven.

In the preferred embodiment of the present invention, even though thecharge charging/discharging elements (C_(Ext1), C_(Ext2)) were arrangedon the outside of the integrated block (36), it can be integrated intothe capacitor switching control unit (40) as shown in FIG. 11.

Now, an explanation will be made about the driving operation of thedriving circuit for the field emission display according to theembodiment of the present invention constructed as described above inwhich the driving circuit has a gate line connected thereto.

FIG. 10 is another embodiment of the present invention. The explanationregarding FIG. 10 is omitted since its circuit construction andoperation are substantially same as that of FIG. 6.

First, in the embodiment of the present invention, it is assumed that inthe initial state, the voltage of the gate line (Gate_Line) is“V_(high)−V_(cap)/2”, and the capacitor lower switching signal(Cap_Low_Switching) is 0V as illustrated in FIGS. 8 and 9.

In FIG. 8, since the capacitor switching control signal(Cap_Switch_Control) is raised to be preceded by a predetermined value(α) more than the gate line selecting control signal (Gate_Control), thesecond high voltage switching element (30) is turned on by the secondhigh voltage controller (34) before than the first high voltageswitching element (28), and when the capacitor low switching signal(Cap_Low_Switching) is raised from “0V” to “V_(cap)”, a charge residenton the charge charging/discharging element (C_(Ext)) is progressivelytransmitted to the gate line (Gate_Line) via the second high voltageswitching element (30), thereby allowing the voltage of the gate line(Gate_Line) to be close to “V_(high)”.

Thereafter, as the gate line selecting control signal (Gate_Control) hasbeen raised, the first high voltage switching element (28) is turned onby the first high voltage element controller (32), and the high voltage(V_(high)) is applied to the gate line (Gate_Line) via the first highvoltage switching element (28). Consequently, the voltage of the gateline (Gate_Line) becomes high voltage (V_(high)) level.

The voltage of the gate line (Gate_Line) continuously maintains the highvoltage level (V_(high)), while the gate line selecting control signal(Gate_Control) maintains the high level (for example, 5V), and thecapacitor low switching signal (Cap_Low_Switching) maintains “V_(cap)”level.

In this state, if the gate line selecting control signal (Gate_Control)and the capacitor low switching signal (Cap_Low_Switching) are droppedbefore than the capacitor switching control signal (Cap_Switch_Control),the second high voltage switching element (30) is turned on while thefirst high voltage switching element (28) is turned off.

Accordingly, the voltage of the gate line (Gate_Line) is dropped. Thatis, since the charge in the gate line (Gate_Line) is transmitted to thecharge charging/discharging element (C_(Ext)) via the second highvoltage switching element (30), the voltage of the gate line (Gate_Line)is returned to its initial voltage (V_(high)−V_(cap)/2).

Now, an explanation will be made about the driving operation accordingto the embodiment of the present invention as described above using anumerical expression.

When the gate line selecting control signal (Gate_Control) becomes ahigh level (that is, 5V), if the capacitor switching control signal(Cap_Switch_Control) is set to be high level (That is, 5V), and thevoltage of the capacitor low switching signal (Cap_Low_Switching) on theend of the charge charging/discharging element (C_(Ext)) raises to“V_(cap)”, the capacitor (C_(Load)) of the gate line (Gate_Line) and thecharge charging/discharging element (C_(Ext)) are charged by the highvoltage (V_(high)). In this time, the capacitor (C_(Load)) and thecharge charging/discharging element (C_(Ext)) are represented by thefollowing equation.

Q _(Total) =C _(Load) ·V _(high) +C _(Ext)(V _(high) −V_(cap))  <Equation 3>

Thereafter, when the gate line selecting control signal (Gate_Control)becomes a low level (that is, 0V), if the capacitor switching controlsignal (Cap_Switch_control) is maintained at its high level (that is,5V), and the capacitor low switching signal (Cap_Low_Switching) becomes0V, the voltage of the gate line (Gate_Line) will be dropped.

At this time, the quantity of charge which is charged on the capacitor(C_(Load)), and the charge charging/discharging element (C_(Ext)) isrepresented by the following Equation 4.

Q _(Total) =C _(Load) ·V _(high) +C _(Ext)(V _(high) −V _(cap))=C_(Load)(2V _(high) −V _(cap)), if C _(Load) =C _(Ext), then=2C_(Load)(V_(high) −V _(cap)/2)=2C _(Load) V _(Low)  <Equation 4>

Accordingly, the voltage of the gate line (Gate_Line) is represented bythe following Equation 5.

V _(Low) =V _(high) −V _(cap)/2  <Equation 5>

According to the embodiment described above, as shown in FIG. 9, thevoltage of the gate line (Gate_Line) is swinging in the voltage scoperanging from “V_(high)−V_(cap)/2” to V_(high). That is, the swing widthof the output voltage for driving the gate line (Gate_Line) is equal to“V_(cap)/2”.

The power consumption at this moment, namely, the power (P_(Load))consumed in charging the capacitor (C_(Load)) of the gate line(Gate_Line), the power (P_(cap)) consumed in swinging the chargecharging/discharging element (C_(Ext)) and the total power consumption(P_(Total)) are represented by equations (6), (7) and (8) respectively.

P _(Load) =N·f·C _(Load) ·V _(high) ·V _(cap)/2  <Equation 6>

Wherein N is the number of the gate lines of the field emission displaypanel, f is the frame frequency, C_(Load) is capacitance of one gateline, V_(high) is the width of the voltage swing in the output terminal,and V_(cap) is the width of the voltage swing of the signal(Cap_Low_Switching) applied to the charge charging/discharging element(C_(Ext)).

P _(cap) =N·f·C _(Ext) ·V _(cap) ²  <Equation 7>

P _(Total) =N·f·C _(Load) ·V _(cap)(V _(high)/2·V _(cap))  <Equation 8>

Herein, from Equation 8, if V_(high)=100V and V_(cap)=40V, then thetotal power consumption (P_(Total)) is obtained from the followingequation.

P _(Total)=3600·N·f·C _(Load)=(36/100)P _(conv)  <Equation 9>

Wherein P_(conv) is the consumption power in the conventional art asshown in Equation 2.

According to the embodiment of the present invention, it can beunderstood that since the swing width of the output voltage is in thescope of “80V” to “100V”, the scope is narrower than that of theconventional art which is ranged from 0V to 100V and that when comparedto the conventional art with respect to only power consumption in theoutput terminal, only 36% of the power is consumed.

According to the present invention as described above, the swing widthof the output voltage can be narrowed, thereby reducing the powerconsumption.

Also, since the voltage applied to the high voltage element is small,the reliability of the driving circuit can be improved. Owing to thereduced power consumption, the heating amount of the driving circuit isalso reduced, and thus the reliability of the device over a heat isimproved. Also, with the reduction of the heating amount, it becomeseasy to package the gate driving circuit.

Further, since it is possible to reduce the size and heating amount ofthe high voltage device, compared to the conventional art, it ispossible to integrate many output terminals into one integrated circuit.

The driving circuit applied to the gate line according to the embodimentof the present invention can also be applied to the cathode line andanode lines.

Although the preferred embodiments of the present invention have beendisclosed for illustrative purposes, the present invention is notlimited to it, and various variations, modifications and additions maybe made without departing from the scope of the present invention.

What is claimed is:
 1. A driving circuit for a field emission displaycomprising: a plurality of cells, each cell being connected to each gateline in an one to one manner; a shift register for sequentiallytransmitting a gate line selecting control signal to said plurality ofcells; a capacitor switching control unit for transmitting a capacitorswitching control signal having a predetermined pulse width to saidplurality of cells; an external capacitor control unit for outputting acapacitor low switching signal having a predetermined pulse width; and acapacitance for performing a charge charging/discharging operation inaccordance with said capacitor low switching signal, wherein said cellscomprise a first switching element formed between a power supplyterminal and the corresponding gate line, for performing a switchingoperation; a second switching element connected to the first switchingelement in serial and to the corresponding gate line, for performing aswitching operation; a first element controller for controlling a flowof charge to the corresponding gate line by switching-controlling thefirst switching element by the control signal for selecting the gateline; and a second element controller for controlling a flow of chargeto the corresponding gate line and the capacitance byswitching-controlling the second switching element by the capacitorswitch control signal; said shift register, said capacitor switchcontrol unit and said plurality of cells being integrated in one block;said capacitance being arranged one or more to be on the outside of theblock.
 2. A driving circuit according to claim 1, wherein said pluralityof cells share said capacitance.
 3. A driving circuit according to claim2, wherein said plurality of cells share one capacitance everyodd-numbered and even-numbered cells.
 4. A driving circuit according toclaim 1, wherein said capacitance arranged to said odd-numbered andeven-numbered cells are alternately driven.
 5. A driving circuitaccording to claim 1, wherein one or more of said capacitance arrangedinto said integrated block.
 6. A driving circuit according to claim 1,wherein the width of said capacitor switching control signal is widerthan that of said gate line selecting control signal.
 7. A drivingcircuit according to claim 1, wherein said first and second switchingelements are composed of high voltage MOS transistor.
 8. A drivingcircuit according to claim 1, wherein when said gate line is driven,said second switching element becomes conductive earlier than said firstswitching element.
 9. A driving circuit according to claim 1, whereinwhen said gate line is driven, said first switching element becomesnon-conductive earlier than said second switching element.
 10. A drivingcircuit according to claim 1, wherein an output voltage of said gateline is controlled by the capacity of said capacitance.
 11. A drivingcircuit according to claim 1, wherein an output voltage of said gateline is controlled by the voltage and waveform applied to thecapacitance.
 12. A driving circuit according to claim 1, wherein whensaid gate line is driven, the width of voltage swing of thecorresponding line is “V_(cap)/2”, wherein V_(cap) is the width ofvoltage swing of the control signal applied to the chargecharging/discharging element.
 13. A driving circuit according to claim1, wherein when said first element controller and said second elementcontroller in response to receive an active signal, for turning on saidfirst switching element and said second switching element, respectively.